ISA_IOW : in STD_LOGIC - ISA_SMEMR: in STD_LOGIC - ISA_SMEMW: in STD_LOGIC - ISA_MEMW: in STD_LOGIC - ISA_MEMR: in STD_LOGIC - ISA_BALE: in STD_LOGIC - ISA_AEN: in STD_LOGIC - ISA_IO16 : out STD_LOGIC - ISA_DATA_EN : out STD_LOGIC - Enable line for Level Shifter IC on Data Bus - ISA_DATA_DIR: out STD_LOGIC - Direction line for Level Shifter IC on Data Bus - ISA_CLK: in STD_LOGIC - ISA_OSC is clock signal coming from ISA BUS PC104 side ISA_DBUS_INOUT : inout STD_LOGIC_VECTOR ( 7 downto 0 )
ISA_ABUS_IN : in STD_LOGIC_VECTOR ( 7 downto 0 ) library UNISIM -use entity main_src is Port ( ALL - Uncomment the following library declaration if instantiating - any Xilinx primitives in this code.
ALL - Uncomment the following library declaration if using - arithmetic functions with Signed or Unsigned values use IEEE.
ALL - use IEEE.STD_LOGIC_ARITH.ALL use IEEE.STD_LOGIC_UNSIGNED.
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